8051 hardware summary
Transkript
8051 hardware summary
8051 hardware summary Burak Galip ASLAN February, 2008 8051 block diagram Burak Galip ASLAN February, 2008 8051 pinouts + 5V Burak Galip ASLAN February, 2008 ports • port 0 : dual-purpose (general-purpose, external memory address and data) • port 1 : dedicated (interfacing to external devices) • port 2 : dual-purpose (general-purpose, external memory address and data) • port 3 : dual-purpose (general-purpose, special features) Burak Galip ASLAN February, 2008 port 3 – special features Burak Galip ASLAN February, 2008 bus control signals • PSEN : Program Store Enable (enables external program memory) • ALE : Address Latch Enable (demultiplexing the address and data bus) • EA : External Access (program execution from external or internal memory, programming of internal PEROM) • RST : Reset (system start-up) Burak Galip ASLAN February, 2008 on-chip oscillator inputs • on-chip oscillator can either be driven by a crystal (~ 12 MHz) or a TTL clock source Burak Galip ASLAN February, 2008 I/O port structure • 4 low-power Schottky TTL loads for ports 1, 2, 3 • 8 LS loads for Port 0 Burak Galip ASLAN February, 2008 pull-up / pull-down resistors Burak Galip ASLAN February, 2008 TTL vs. CMOS Transistor-Transistor Logic • BJTs (Bipolar Junction Transistor) + resistors • low power consumption (more power consumption at rest, however it does not increase much with clock speed compared to CMOS) • easier design rules • slower Complementarysymmetry Metal-OxideSemiconductor • MOSFETs (Metal-OxideSemiconductor FieldEffect-Transistors) • high power consumption (it increases dramatically with clock speed) • harder to design • faster Burak Galip ASLAN February, 2008 TTL vs. CMOS (cont’d) CMOS NAND gate TTL NAND gate Burak Galip ASLAN February, 2008 memory organization • 128B internal RAM • 4KB ROM • can be expanded to 64KB code memory and 64KB data memory • registers and I/O ports are memory-mapped and accessible like any other memory location • stack resides within the internal RAM (unlike microprocessors using external RAM for stack) Burak Galip ASLAN February, 2008 internal RAM Burak Galip ASLAN February, 2008 general-purpose RAM direct addressing 80B MOV A, 5FH MOV R0, #5FH MOV A, @R0 indirect addressing • 00H – 2FH can be used as similar (80B + 48B = 128B) • any location in the general-purpose RAM can be accessed freely using direct and indirect addressing modes Burak Galip ASLAN February, 2008 bit-addressable RAM • 210 bit-addressable locations • individually accessing bits SETB 67H microcontroller MOV A, 2CH ORL A, #10000000B MOV 2CH, A microprocessor Burak Galip ASLAN February, 2008 register banks PSW context-switching default by system reset MOV A, R5 register addressing 1B MOV A, 05H direct addressing 2B Burak Galip ASLAN February, 2008 Special Function Registers • 21 SFRs • some of them are both bitaddressable and byteaddressable SETB E0H E0H : bit-address of the accumulator E0H : byte-address of the accumulator P0 : 80H (80H – 87H) {10000xxx} Burak Galip ASLAN February, 2008 Program Status Word Burak Galip ASLAN February, 2008 CarrY flag of PSW arithmetic operations ADD A, #1 CY is set ; A = FFH boolean accumulator ANL C, 25H result is stored in CY Burak Galip ASLAN February, 2008 Auxiliary Carry flag of PSW checks the lower nibble of result in BCD addition XXXX 1010 if {0AH – OFH} AC is set DA A ; Decimal Adjust Accumulator (result back in range 9) DA must follow the addition Burak Galip ASLAN February, 2008 Flag 0 of PSW general-purpose flag bit, F0 (for user applications) Burak Galip ASLAN February, 2008 Register bank Select bits of PSW SETB RS1 SETB RS0 MOV A, R7 Burak Galip ASLAN February, 2008 OVerflow flag of PSW • when unsigned numbers are added or subtracted, OV can be ignored • when signed numbers are added or subtracted, results out of {-128 to +127} sets OV Burak Galip ASLAN February, 2008 Parity bit of PSW • P bit is automatically set or cleared with each machine cycle (even parity check on accumulator) • if [number of 1’s in accumulator] + 1 = even then (P = 1) Burak Galip ASLAN February, 2008 B register MUL AB ; A(8-bit) X B(8-bit) = 16-bit result (high-byte, low-byte) DIV AB ; A(8-bit) / B(8-bit) = 8-bit integer result, 8-bit remainder it can also be used as a generalpurpose scratch-pad register Burak Galip ASLAN February, 2008 Stack Pointer 32B SS • push -> first SP+1, then write data • pop -> first read data, then SP-1 • default by system reset : 07H MOV SP, #5FH ! ! ! ; beginning address of stack = 60H be very careful of what you are doing if you do not initialize your own stack space but still use context switching, and PUSH, POP, ACALL, LCALL, RET, RETI instructions on stack space (SS) Burak Galip ASLAN February, 2008 Data PoinTeR high-byte - DPH low-byte - DPL • accessing external code or external data memory MOV A, #55H ; immediate addressing MOV DPTR, #1000H ; immediate addressing MOVX @DPTR, A ; indirect addressing 55H Burak Galip ASLAN February, 2008 Port registers • ports 0,2 and 3 may not be available for I/O if external memory is used or if some 8051 special features (interrupts, serial ports, etc.) are used • P1.2 to P1.7 are always available for general purpose I/O lines WAIT: SETB P1.7 CLR P1.7 JB P1.5, WAIT “1” device busy “0” device ready Burak Galip ASLAN February, 2008 Timer registers high-byte – TH1 high-byte – TH0 low-byte – TL1 low-byte – TL0 Timer MODe register Timer CONtrol register • two 16-bit timer/counters • Timer 0 : {TH0, TL0} • Timer 1 : {TH1, TL1} • only TCON is bit-addressable Burak Galip ASLAN February, 2008 Serial port registers • on-chip serial port for communicating with serial devices • Serial data BUFfer (SBUF) holds both the transmit data (writing to buffer) and the receive data (reading from buffer) • Various modes of operation on bitaddressable Serial port CONtrol register (SCON) Burak Galip ASLAN February, 2008 Interrupt registers • 5-source, 2-priority level interrupt structure • interrupts are disabled as default by system reset • should be enabled by writing to the Interrupt Enable register (IE) • priority level is set through the Interrupt Priority register (IP) Burak Galip ASLAN February, 2008 Power CONtrol register Burak Galip ASLAN February, 2008 IDLe mode • an instruction that sets IDL bit will be the last instruction executed before entering idle mode • CPU status preserved, all register contents are maintained • port pins retain their logic levels • ALE and PSEN are held high • idle mode is terminated by any enabled interrupt or by system reset, either condition clears the IDL bit Burak Galip ASLAN February, 2008 Power Down mode • an instruction that sets PD bit will be the last instruction executed before entering power down mode • on-chip oscillator stopped • all function are stopped • all on-chip RAM contents are retained • port pins retain their logic levels • ALE and PSEN are held low • only exit is system reset • VCC can be as low as 2V in power down mode Burak Galip ASLAN February, 2008 external memory • 64K external code memory space and 64K external data memory space can be made available by 8051 architecture • when external memory is used P0 is unavaliable as an I/O port • P0 becomes a multiplexed address (A0-A7) and data (D0-D7) bus with ALE latching the low-byte of the address at the beginning of each memory cycle • if MOVX instructions are never used ALE pulses consistently at 1/6 of crystal frequency • if MOVX instruction is used both ALE and PSEN pulses are skipped once on the RD line to enable the RAM Burak Galip ASLAN February, 2008 multiplexing address and data buses Burak Galip ASLAN February, 2008 accessing external code memory Burak Galip ASLAN February, 2008 read timing for external code memory Burak Galip ASLAN February, 2008 accessing external data memory Burak Galip ASLAN February, 2008 accessing external data memory (cont’d) SETB P2.0 MOVX instruction MOVX A, @DPTR SETB P2.1 MOV R0, #FFH MOVX A, @R0 read 03FFH Burak Galip ASLAN February, 2008 address decoding Burak Galip ASLAN February, 2008 external memory (cont’d) • increment RAM location by 1: it takes 1 instruction and 1 instruction cycles for internal RAM it takes 4 instructions and 7 instruction cycles for external RAM • external memory is ~ 7 times slower • size: internal RAM is limited to 128B external RAM up to 64KB Burak Galip ASLAN February, 2008 overlapping the external code and data spaces Burak Galip ASLAN February, 2008 von Neumann architecture stored program concept program can modify themselves on the run program faults can effect other programs, operating system leading to ‘crash’es memory protection and access control mechanisms against malware von Neumann bottleneck caches, branch prediction algorithms Burak Galip ASLAN February, 2008 Hardvard architecture • separate storage and signal pathways for instructions and data • modifying programs is entirely an offline process • instruction memory often wider than data memory • speed is gained at the expense of more complex electrical circuitry • caches (high cost) for memory bound problem • specialized DSPs (audio/video, etc.), small microcontrollers (PIC, etc.) • modern high-performance CPU designs incorporate aspects of both von Neumann and Harvard architectures Burak Galip ASLAN February, 2008 ReSeT operation • 8051 is reset by holding RST high for two machine cycles and then returning it low power-on reset manual reset Burak Galip ASLAN February, 2008 Register values after system ReSeT Burak Galip ASLAN February, 2008 summary • 8051 architecture and layout • memory organization • Special Function Registers • external memory Burak Galip ASLAN February, 2008 references http://www.personal.dundee.ac.uk/~gathomso/EG2103/pull-up.doc http://www.8052.com/tutmemor.phtml Burak Galip ASLAN February, 2008